74LS112 Dual J-K Negative Edge Triggered Flip Flop IC. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. This versatile flip-flop can perform as toggle flip-flop by tying J and K high. The 74S112 is characterized for operation from 0 to 70°C.

Package Includes:

1 x 74112 (74LS112) Dual J-K Negative Edge Triggered Flip Flop IC